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preliminary rev. 0.25 7/09 copyright ? 2009 by silicon laboratories SI590/591 SI590/591 1 ps m ax j itter c rystal o scillator (xo) (10 mh z to 525 mh z ) features applications description the SI590/591 xo utilizes silicon laboratories? advanced dspll ? circuitry to provide a low jitter clock at high frequencies. the SI590/591 is available with any-rate output frequency from 10 to 525 mhz. unlike a traditional xo, where a unique crystal is required for each output frequency, the SI590/591 uses one fixed crystal to provide a wide range of output frequencies. this ic based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. the SI590/591 ic based xo is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. functional block diagram ? available with any-rate output frequencies from 10 mhz to 525 mhz ? 3rd generation dspll ? with superior jitter performance: 1 ps max jitter ? better frequency stability than saw- based oscillators ? internal fundamental mode crystal ensures high reliability ? available cmos, lvpecl, lvds, and cml outputs ? 3.3, 2.5, and 1.8 v supply options ? industry-standard 5 x 7 mm package and pinout ? pb-free/rohs-compliant ? ?40 to +85 oc operating temperature range ? sonet/sdh (oc-3/12/48) ? networking ? sd/hd sdi/3g sdi video ? test and measurement ? storage ? fpga/asic clock generation fixed frequency xo any-rate 10?525 mhz dspll ? clock synthesis v dd clk+ clk? gnd oe 17 k * 17 k * *note: output enable high/low options available ? see ordering information ? ? ordering information: see page 6. pin assignments: see page 5. (top view) si5602 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc 1 2 3 6 5 4 gnd nc v dd clk nc oe 1 2 3 6 5 4 gnd nc v dd clk+ clk? oe SI590 (lvds/lvpecl/cml) SI590 (cmos) si591 (lvds/lvpecl/cml) www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 2 preliminary rev. 0.25 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max units supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 1.8 v option 1.71 1.8 1.89 supply current i dd output enabled lvpecl cml lvds cmos ? ? ? ? 110 100 90 80 125 110 100 90 ma tristate mode ? 60 75 output enable (oe) 2 v ih 0.75 x v dd ?? v v il ??0.5 operating temperature range t a ?40 ? 85 oc notes: 1. selectable parameter specified by part number. see section 3. "ordering information" on page 6 for further details. 2. oe pin includes an internal 17 k ? pullup resistor to v dd for output enable active high or a 17 k ? pull-down resistor to gnd for output enable active low. see 3. "ordering information" on page 6. table 2. clk output frequency characteristics parameter symbol test condition min typ max units nominal frequency 1,2 f o lvpecl/lvds/cml 10 ? 525 mhz cmos 10 ? 160 initial accuracy f i measured at +25 c at time of shipping ? 1.5 ? ppm total stability note 3, second option code ?c? ? ? 30 ppm note 4, second option code ?b? ? ? 50 ppm note 4, second option code ?a? ? ? 100 ppm temperature stability second option code ?c? ? ? 20 ppm second option code ?b? ? ? 25 ppm second option code ?a? ? ? 50 ppm powerup time 5 t osc ??10ms notes: 1. see section 3. "ordering informat ion" on page 6 for further details. 2. specified at time of order by part number. 3. includes initial accuracy, te mperature, shock, vibration, power supply an d load drift, and 10 years aging at 40 c. see 3. "ordering information" on page 6. 4. includes initial accuracy, te mperature, shock, vibration, power supply an d load drift, and 15 years aging at 70 c. see 3. "ordering information" on page 6. 5. time from powerup or tristate mode to f o . www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 preliminary rev. 0.25 3 table 3. clk output levels and symmetry parameter symbol test condition min typ max units lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.55 ? 0.95 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.5 0.7 0.9 v pp cml output option 2 v o mid-level ? v dd ? 0.75 ? v v od swing (diff) 0.70 0.95 1.20 v pp cmos output option 3 v oh 0.8 x v dd ? v dd v v ol ??0.4 rise/fall time (20/80%) t r, t f lvpecl/lvds/cml ? ? 350 ps cmos with c l =15pf ? 2 ? ns symmetry (duty cycle) sym lvpecl: v dd ? 1.3 v (diff) lvds: 1.25 v (diff) cmos: v dd /2 45 ? 55 % notes: 1. 50 ? to v dd ? 2.0 v. 2. r term = 100 ? (differential). 3. c l = 15 pf. sinking or sourcing 12 ma for v dd = 3.3v, 6ma for v dd = 2.5v, 3ma for v dd = 1.8 v. table 4. clk output phase jitter parameter symbol test condition min typ max units phase jitter (rms) 1 for 50 mhz < f out < 525 mhz (lvpecl/lvds/cml) ? j 12 khz to 20 mhz ? 0.5 1.0 ps phase jitter (rms) 2 for 50 mhz < f out < 160 mhz (cmos) ? j 12 khz to 20 mhz ? 0.6 1.0 ps notes: 1. differential modes lvpecl/lvds/cml. 3.3 and 2.5 v supply voltage options only. 2. single-ended cmos output phase jitter measured using 33 ? series termination into 50 ? phase noise test equipment. 3.3 v supply voltage option only. table 5. clk output period jitter parameter symbol test condition min typ max units period jitter* j per rms ? ? 3 ps peak-to-peak ? ? 35 *note: any output mode, incl uding cmos, lvpecl, lvds, cml. n = 1000 cycles . refer to an279 fo r further information. www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 4 preliminary rev. 0.25 table 6. absolute maximum ratings 1 parameter symbol rating units maximum operating temperature t amax 85 oc supply voltage, 1.8 v option v dd ?0.5 to +1.9 v supply voltage, 2.5/3.3 v option v dd ?0.5 to +3.8 v input voltage (any input pin) v i ?0.5 to v dd + 0.3 volts storage temperature t s ?55 to +125 oc esd sensitivity (hbm, per jesd22-a114) esd 2500 v soldering temperature (pb-free profile) 2 t peak 260 oc soldering temperature time @ t peak (pb-free profile) 2 t p 20?40 seconds notes: 1. stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. functional operation or specification co mpliance is not implied at these conditions. exposure to maximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020c. refer to si5xx packaging faq available for download at www.silabs.com/vcxo for further information, including soldering profiles. table 7. environmental compliance the SI590/591 meets the following qualification test requirements. parameter conditions/test method mechanical shock mil-std-883g, method 2002.3 b mechanical vibration mil-std-883g, method 2007.3 a solderability mil-std-8 83g, method 203.8 gross & fine leak mil-std-883g, method 1014.7 resistance to solvents mil-std-883g, method 2015 www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 preliminary rev. 0.25 5 2. pin descriptions table 8. pinout for SI590 series pin symbol lvds/lvpecl/cml function cmos function 1oe* no connection make no external connection to this pin output enable 2oe* output enable no connection make no external connection to this pin 3 gnd electrical and case grou nd electrical and case ground 4 clk+ oscillator output oscillator output 5 clk? complementary output no connection make no external connection to this pin 6v dd power supply voltage power supply voltage *note: oe pin includes an internal 17 k ? pullup resistor to v dd for output enable active high or a 17 k ? pulldown resistor to gnd for output enable active low. see 3. "ordering information" on page 6. table 9. pinout for si591 series pin symbol lvds/lvpecl/cml function 1 oe* output enable 2 no connection make no external connection to this pin no connection make no external connection to this pin 3 gnd electrical and case ground 4 clk+ oscillator output 5 clk? complementary output 6v dd power supply voltage *note: oe pin includes an internal 17 k ? pullup resistor to v dd for output enable active high or a 17 k ? pulldown resistor to gnd for output enable active low. see 3. "ordering information" on page 6. 1 2 3 6 5 4 gnd nc v dd clk nc oe (top view) 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc 1 2 3 6 5 4 gnd nc v dd clk+ clk? oe SI590 lvds/lvpecl/cml SI590 cmos si591 lvds/lvpecl/cml www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 6 preliminary rev. 0.25 3. ordering information the SI590/591 xo su pports a variety of options incl uding frequency, temp erature stability, ou tput forma t, and v dd . specific device configurations are programmed into the SI590/591 at time of shipment. configurations can be specified using the part number conf iguration chart below. silicon labora tories provides a web browser-based part number configuration utility to simplify this proc ess. refer to www.silabs.com/vcxopartnumber to access this tool and for further ordering instructions. the SI590 and si591 xo series are supplied in an industry-standard, rohs compliant, 6-pad, 5 x 7 mm package. the si591 seri es supports an alternate oe pinout (pin #1) for lvpecl, lvds, and cml output formats. see tables 8 and 9 for the pinout differences betw een the SI590 and si591 series. figure 1. part number convention 59x x xxxmxxx x 1 st option code v dd output format output enable polarity a 3.3 lvpecl high b 3.3 lvds high c 3.3 cmos high d3.3cml high e 2.5 lvpecl high f 2.5 lvds high g 2.5 cmos high h2.5cml high j 1.8 cmos high k1.8cml high m 3.3 lvpecl low n3.3lvds low p3.3cmos low q3.3cml low r 2.5 lvpecl low s2.5lvds low t2.5cmos low u2.5cml low v1.8cmos low w1.8cml low note : cmos available to 160 mhz. d g r frequency (e.g., 148m352 is 148.352 mhz) available frequency range is 10 to 525 mhz. the position of ?m? shifts to denote higher or lower frequencies. if the frequency of interest requires greater than 6 digit resolution, a six digit code will be assigned for the specific frequency. tape & reel packaging blank = trays operating temp range (c) g ?40 to +85c part revision letter 590 or 591 xo product family example p/n: 590bb148m352dgr is a 5 x 7 xo in a 6 pad package. the frequency is 148.352 mhz, with a 3.3 v supply, lvds output, and output enable active high polarity. overall stability is specifed as 50 ppm. the device is specified for ?40 to +85 c ambien t temperature range operation and is shipped in tape and reel format. 2 nd option code code total stablility (ppm, max, ) temperature stablility (ppm, max, ) a 100 50 b 50 25 c 30 20 www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 preliminary rev. 0.25 7 4. outline diagram and suggested pad layout figure 2 illustrates the package details fo r the SI590/591. table 10 lists the valu es for the dimensions shown in the illustration. figure 2. SI590/591 outline diagram table 10. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 d 7.00 bsc d1 4.30 4.40 4.50 e 2.54 bsc. e 5.00 bsc. e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 p 1.80 ? 2.60 r 0.70 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.50 www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 8 preliminary rev. 0.25 5. SI590/si591 ma rk specification figure 3 illustrates the mark specif ication for the SI590/si591. ta ble 11 lists the line information. figure 3. mark specification table 11. si53x top mark description line position description 1 1?10 ?silabs?+ part family number, 59 x (first 3 characters in part number) 2 1?10 SI590, si591: option1 + option2 + freq(7) + temp SI590/si591 w/ 8-digit resolution: option1 + option2 + confignum(6) + temp 3 trace code position 1 pin 1 orientation mark (dot) position 2 product revision (d) position 3?6 tiny trace code (4 alphanumeric charac ters per assembly release instructions) position 7 year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9) position 8?9 calendar work week number (1?53), to be assigned by assembly site position 10 ?+? to indicate pb-free and rohs-compliant silabs 123 123 4 5 6 r t t t t y w w + 1 2 3 4 5 6 7 8 9 0 www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 preliminary rev. 0.25 9 6. 6-pin pcb land pattern figure 4 illustrates the 6-pin pcb land pa ttern for the SI590/ 591. table 12 lists the values for the dimensions shown in the illustration. figure 4. SI590/591 pcb land pattern . table 12. pcb land pattern dimensions (mm) dimension min max d2 5.08 ref e 2.54 bsc e2 4.15 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1.70 typ y2.15 ref zd ? 6.78 ze ? 6.30 notes: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design based on ipc-7351 guidelines. 3. all dimensions shown are at ma ximum material condition (mmc). 4. controlling dimension is in millimeters (mm). www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 preliminary rev. 0.25 10 d ocument c hange l ist revision 0.2 to revision 0.25 ? total stability maximum changed to 30 in table 2 on page 2. ? total stability maximum cha nged to 30 in figure 1 on page 6. www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 preliminary rev. 0.25 11 n otes : www.datasheet.co.kr datasheet pdf - http://www..net/
SI590/591 12 preliminary rev. 0.25 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. www.datasheet.co.kr datasheet pdf - http://www..net/

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